Test MP+dmb.sy+pos-ctrl-ctrl-[ws-rf]-ctrlisb

AArch64 MP+dmb.sy+pos-ctrl-ctrl-[ws-rf]-ctrlisb
"DMB.SYdWW Rfe PosRR DpCtrldR DpCtrldW WsLeave RfBack DpCtrlIsbdR Fre"
Cycle=Rfe PosRR DpCtrldR DpCtrldW WsLeave RfBack DpCtrlIsbdR Fre DMB.SYdWW
Relax=
Safe=Rfe Fre PosRR DMB.SYdWW DpCtrldW DpCtrldR DpCtrlIsbdR [WsLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe PosRR DpCtrldR DpCtrldW WsLeave RfBack DpCtrlIsbdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z; 1:X6=a; 1:X9=x;
2:X1=a;
}
 P0          | P1           | P2          ;
 MOV W0,#1   | LDR W0,[X1]  | MOV W0,#2   ;
 STR W0,[X1] | LDR W2,[X1]  | STR W0,[X1] ;
 DMB SY      | CBNZ W2,LC00 |             ;
 MOV W2,#1   | LC00:        |             ;
 STR W2,[X3] | LDR W3,[X4]  |             ;
             | CBNZ W3,LC01 |             ;
             | LC01:        |             ;
             | MOV W5,#1    |             ;
             | STR W5,[X6]  |             ;
             | LDR W7,[X6]  |             ;
             | CBNZ W7,LC02 |             ;
             | LC02:        |             ;
             | ISB          |             ;
             | LDR W8,[X9]  |             ;
Observed
    y=1; x=1; a=1; 1:X8=1; 1:X7=1; 1:X2=0; 1:X0=1;